IITB RISC Pipelined
IITB RISC Pipelined
Check the github repository here: IITB RISC Pipelined
What is IITB-RISC?
IITB-RISC is a 16-bit very simple computer developed for the teaching that is based on the Little Computer Architecture. The IITB-RISC-22 is a 16-bit computer system with 8 registers. It follows the standard 6 stage pipeline:
- Instruction fetch
- Instruction decode
- Register read
- Execute
- Memory access
- Write back
The architecture is optimized for performance using hazard mitigation techniques namely:
- Forwarding
- Branch prediction