IITB RISC Multicycle

Sunday. March 14, 2021

IITB-RISC Multicycle

Check the github repository here: IITB RISC Multicycle

What is IITB-RISC?

• IITB-RISC is a multi-cycle processor with the Instruction Set Architecture provided here.
• IITB-RISC is a 16-bit very simple computer developed for the teaching that is based on the Little Computer Architecture.
• The IITB-RISC-22 is a 16-bit computer system with 8 registers.

IITB-RISC Instruction Set Architecture

• The IITB-RISC is an 8-register, 16-bit computer system.
• It has 8 general-purpose registers (R0 to R7).
• Register R7 is always stores Program Counter.
• All addresses are short word addresses (i.e., address 0 corresponds to the first two bytes of main memory, address 1 corresponds to the second two bytes of main memory, etc.).
• This architecture uses condition code register which has two flags Carry flag ( C ) and Zero flag (Z).
• There are three machine-code instruction formats (R, I, and J type) and a total of 17 instructions.